```// ************************************************************************** //
//                                                                            //
//    eses                   eses                                             //
//   eses                     eses                                            //
//  eses    eseses  esesese    eses   Embedded Systems Group                  //
//  ese    ese  ese ese         ese                                           //
//  ese    eseseses eseseses    ese   Department of Computer Science          //
//  eses   eses          ese   eses                                           //
//   eses   eseses  eseseses  eses    University of Kaiserslautern            //
//    eses                   eses                                             //
//                                                                            //
// ************************************************************************** //
// This cyclic circuit is due to C.R. McCaw, “Loops in Directed Combinational //
// Switching Networks,” Engineer’s Thesis, Stanford University, 1963. It is   //
// described on page 9 in Riedel's thesis [Ried04]. McCaw argues that his     //
// cyclic circuit has fewer gates than any acyclic circuit. The assertions    //
// show a possible acyclic circuit that is proved to be equivalent by the     //
// exhaustive simulation given by the driver below.                           //
// ************************************************************************** //

module McCaw(event ?a,?b,?c,?d,?x,y1,y2) {
always{
y1 = a | b |  x & (c | d | !x & y2);
y2 = c | d | !x & (a | b |  x & y1);
if(x) {
assert(y1 == (a | b | c | d));
assert(y2 == (c | d));
} else {
assert(y1 == (a | b));
assert(y2 == (a | b | c | d));
}
}
} drivenby {
bv{5} w;
for(i=0..31) {
pause;
w = nat2bv(i,5);
a = w{0};
b = w{1};
c = w{2};
d = w{3};
x = w{4};
}
}
```