AbacusState holds the information of the memory contents of an Abacus system after executing an instruction, i.e.,

• instr is the instruction that has generated this state
• prgCounter is the value of the program counter
• overflwReg is the content of the overflow register of Abacus
• sclRegs[i] holds the content of the scalar register i, which has type byte[] whose length is DataWidth/8
• dataCache is an array of cacheblocks
• mainMem is the main memory, i.e., an array of blocks (since the memory transfer to the data cache is done in blocks)
• branchTaken indicates whether the instruction that generated this state was a conditional branch and whether it was taken or not (None:no branch; Some true: branch that was taken; Some false branch that was not taken)
• wasCacheHit indicates whether the instruction that generated this state was a cache hit (Some true), a cache miss (Some false), or no memory instruction (None).
• cacheHits counts the number of cache hits so far including this instruction
• cacheMisses counts the number of cache misses so far including this instruction
• writeBacks counts the number of write backs so far including this instruction (this is the number of replaced dirty blocks)