This file implements functions for translating expressions of finite type to an equivalent circuit representation. The overall idea is that the circuit is generated as a side effect when calling a generator function with input bitvectors. The generator function is thereby given the input and output bitvectors as BoolExpr list.

The module Clearer contains transformations to clear parts of an AIF System or to remove guarded action which have a special form.

This module contains transformations to make equations from the guarded actions. That means that every cell (not QName) is written by exactly one guarded action which has the guard true,i.e. it is assigned in every step. Obviously, such an guarded action must be contained in the 'main' part, because otherwise it would not be executed in every step. Furthermore, the guarded action can be an immediate or a delayed one. If a cell is assigned by a delayed guarded action, the cell must additionally be initalized by an immediate action in the 'init' part. There is also an optimized generation of equations which works for hardware synthesis and does not build equations for (some) delayed actions. The result can be handled in a better by other backend tools. (e.g. xilinx tools)

This file implements ...

Eliminate compound data types (arrays and tuples). - expressions of type (Qtup tyL) are reduced to TupOfExprL[e1,...,en] - select expressions only have constant indices After the reduction, array access and tuple access can be also transformed to new variable names, which is needed to completely eliminate the types from the system description. There are two different algorithms for the expansion of compound types on left-hand sides: The first way makes case distinctions on the index expressions by enumerating the possible indices. The second approach enumerates the possible letues of the variables that occur in the index expressions, which is more efficient, since the knowledge that some variables are fixed to a certain constant is propagated by the substitution(instead of repeating useless case distinctions).

This module implements scheduling algorithms which are applied to general scheduling problems as described by the data type in this module. Acyclic dataflow graphs and basic blocks can be easily mapped to these problems, which additionally allow to add runtimes and required ressources for each node.